Metric Noise Resource (MNR)

Motivation

The Metric-Noise-Resource (MNR) methodology was introduced in 2022 by M. Fellous-Asiani et al. [1] in the context of the Quantum Energy Initiative [2]. The authors motivate the creation of this methodology by the need for a multi-level approach to understand and optimize the resource consumption of quantum computers. As explained by the authors, such an approach requires a strong knowledge of quantum processors at a physical level (e.g., quantum control) and at a software level (e.g., quantum error correction and quantum algorithms). This methodology aims to obtain a clear view of how resources will scale with the size of the computational task.

Methodology

The MNR methodology aims to minimize the resources \(\mathcal{R}\) required by a quantum computer to reach a specific target metric \(\mathcal{M}\) and to identify/analyse non-trivial trade-offs between the parameters under study. This minimization is done with respect to the determined control parameters.

The MNR methodology comprises several components (see figure for the dependency between the main components):

Component dependancy in the Metric Noise Resource (MNR) methodology.

The resource efficiency \(\eta = \mathcal{M} / \mathcal{R}\) is a ratio between the metric \(\mathcal{M}\) and the resources \(\mathcal{R}\) (inspired by the Flops/Watt efficiency metric used in the Green500 ranking). The MNR methodology aims to minimize the resources \(\mathcal{R}\) required to reach a specific target metric \(\mathcal{M}\).

Implementation Examples

Different examples using this methodology are given in the initial paper [1]. These examples use simplified models to provide insights about resource consumption scaling.

Noisy single-qubit gate implementation (quantum-level)

Section III. A of [1] minimizes the power consumption of quantum gates to reach a satisfying fidelity. It studies the trade-offs between:

The following parameters are considered:

Noisy single-qubit gate implementation (macroscopic-level)

Section III. B of [1] minimizes the power consumption, including higher-level controls and the cryostat. It studies the trade-offs between:

The following parameters are considered:

Circuit compression degree

Section IV of [1] studies the degree of compression of the quantum circuit and its impact on the power consumption of the quantum computer. It highlights the trade-offs between:

As the circuit gets compressed, its fidelity increases because qubits have only short idling times. However, running multiple gates at once increases the system’s power consumption.

The following parameters are considered:

Fault-tolerant factorization

Section V of [1] studies the potential advantage of a quantum computer implementing Shor’s algorithm using the Steane code (a fault-tolerant quantum error correction code). It highlights the trade-offs between:

Interestingly, the authors show that it is sometimes energetically more interesting to put qubits at a higher temperature and compensate with the quantum error correction code. They also show that in a specific regime, the quantum computer could factor RSA using more time than a classical computer, but consuming less energy.

The following parameters are considered:

References

  1. [1]M. Fellous-Asiani, J. H. Chai, Y. Thonnart, H. K. Ng, R. S. Whitney, and A. Auffèves, “Optimizing Resource Efficiencies for Scalable Full-Stack Quantum Computers,” PRX Quantum, vol. 4, no. 4, Oct. 2023, doi: 10.1103/prxquantum.4.040319. [Online]. Available at: http://dx.doi.org/10.1103/PRXQuantum.4.040319
  2. [2]A. Auffèves, “Quantum Technologies Need a Quantum Energy Initiative,” PRX Quantum, vol. 3, no. 2, Jun. 2022, doi: 10.1103/prxquantum.3.020101. [Online]. Available at: http://dx.doi.org/10.1103/PRXQuantum.3.020101